Symbolic Netlist

Module Summary


Netlist By Part


T__VME64_P1  Backplane.BAP1 (BKP1):
T__VME64_P2R  Backplane.BAP2 (BKP2):
T__ROD_J0P0  Backplane.BAP0 (BKP0):
T__ROD_J5P5  Backplane.BAP5 (BKP5):
T__ROD_J6P6  Backplane.BAP6 (BKP6):
T__CDC_POS  Backplane.V5_CDC0 (BKCDC1):
T__CDC_POS  Backplane.V5_CDC1 (BKCDC2):
T__CDC_POS  Backplane.V5_CDC2 (BKCDC3):
T__CDC_POS  Backplane.V5_CDC3 (BKCDC4):
T__CDC_POS  Backplane.V5_CDC4 (BKCDC5):
T__CDC_POS  Backplane.V5_CDC5 (BKCDC6):
T__CDC_POS  Backplane.V5_CDC6 (BKCDC7):
T__CDC_POS  Backplane.V3_CDC0 (BKCDC8):
T__CDC_POS  Backplane.V3_CDC1 (BKCDC9):
T__CDC_POS  Backplane.V3_CDC2 (BKCDC10):
T__CDC_POS  Backplane.V3_CDC3 (BKCDC11):
T__CDC_POS  Backplane.V3_CDC4 (BKCDC12):
T__CDC_POS  Backplane.V3_CDC5 (BKCDC13):
T__CDC_POS  Backplane.V3_CDC6 (BKCDC14):
T__TDC_POS  Backplane.V5_TDC0 (BKTDC1):
T__TDC_POS  Backplane.V3_TDC0 (BKTDC2):
T__XOSC_25M  ClockGeneration.OscT_HPU (CGX1):
T__XOSC_25M  ClockGeneration.OscT_BASE (CGX2):
T__XOSC_50M  ClockGeneration.OscT_VME (CGX3):
T__XOSC_SMT_25M  ClockGeneration.OscS_HPU (CGX4):
T__XOSC_SMT_25M  ClockGeneration.OscS_BASE (CGX5):
T__XOSC_SMT_50M  ClockGeneration.OscS_VME (CGX6):
T__R30  ClockGeneration.STerm_Osc_HPU (CGR1):
T__R30  ClockGeneration.STerm_Osc_BASE (CGR2):
T__R30  ClockGeneration.STerm_BOOT_CLK (CGR3):
T__SN74CBTLV3253  ClockGeneration.Mux_RCLK (CGU12):
T__SN74CBTLV3253  ClockGeneration.Mux_SCLK (CGU13):
T__SN74CBTLV3253  ClockGeneration.Mux_TCLK (CGU14):
T__SN74CBTLV3253  ClockGeneration.Mux_DCLK (CGU15):
T__SN74CBTLV3253  ClockGeneration.Mux_DC_CLK (CGU16):
T__SN74CBTLV3253  ClockGeneration.Mux_DX_CLK (CGU17):
T__SN74CBTLV3253  ClockGeneration.Mux_HPU_CLK (CGU18):
T__SN74CBTLV3253  ClockGeneration.Mux_SYN_BASE (CGU19):
T__SN74CBTLV3253  ClockGeneration.SMux_RCLK (CGU20):
T__SN74CBTLV3253  ClockGeneration.SMux_TCLK (CGU21):
T__SN74CBTLV3253  ClockGeneration.SMux_HPU_CLK (CGU22):
T__SN74CBTLV3253  ClockGeneration.SMux_SYN_BASE (CGU23):
T__W170_01  ClockGeneration.Mpy_IRCLK (CGU24):
T__W170_01  ClockGeneration.Mpy_ISCLK (CGU25):
T__W170_01  ClockGeneration.Mpy_ITCLK (CGU26):
T__R30  ClockGeneration.STerm_Mpy_IRCLK (CGR13):
T__R30  ClockGeneration.STerm_Mpy_ISCLK (CGR14):
T__R30  ClockGeneration.STerm_Mpy_ITCLK (CGR15):
T__CDC2510  ClockGeneration.Drv_RCLK0 (CGU31):
T__CDC2516  ClockGeneration.Drv_SCLK (CGU32):
T__CDC2510  ClockGeneration.Drv_TCLK (CGU33):
T__CDC2510  ClockGeneration.Drv_DCLK (CGU34):
T__CDC2516  ClockGeneration.Drv_DC_CLK (CGU35):
T__CDC2516  ClockGeneration.Drv_DX_CLK (CGU36):
T__CDC2510  ClockGeneration.Drv_HPU_CLK (CGU37):
T__CDC2510  ClockGeneration.Drv_DPU_CLK (CGU38):
T__CDC2510  ClockGeneration.Drv_DXINT_CLK (CGU39):
T__CDC2510  ClockGeneration.Drv_VME_CLK (CGU40):
T__SN65LVDS1  ClockGeneration.Drv_BP_RCLKO (CGU41):
T__SN65LVDS1  ClockGeneration.Drv_BP_SCLKO (CGU42):
T__SN65LVDS1  ClockGeneration.Drv_BP_TCLKO (CGU43):
T__SN65LVDS1  ClockGeneration.Drv_BP_DCLKO (CGU44):
T__SN65LVDS9637B  ClockGeneration.Rcv_BP_RCLKI (CGU45):
T__SN65LVDS9637B  ClockGeneration.Rcv_BP_TCLKI (CGU46):
T__SN65LVDS9637B  ClockGeneration.Rcv_FP_RCLKI (CGU47):
T__SN65LVDS9637B  ClockGeneration.Rcv_FP_TCLKI (CGU48):
T__CDC2510  ClockGeneration.Drv_RCLK1 (CGU49):
T__R110  ClockGeneration.DTerm_BP_RCLKI (CGR16):
T__R110  ClockGeneration.DTerm_BP_TCLKI (CGR17):
T__R110  ClockGeneration.DTerm_FP_RCLKI (CGR18):
T__R110  ClockGeneration.DTerm_FP_TCLKI (CGR19):
T__R30  ClockGeneration.STerm_BP_RCLKI (CGR20):
T__R30  ClockGeneration.STerm_BP_TCLKI (CGR21):
T__R30  ClockGeneration.STerm_FP_RCLKI (CGR22):
T__R30  ClockGeneration.STerm_FP_TCLKI (CGR23):
T__R30  ClockGeneration.STerm_DERIVED_BASE (CGR24):
T__C10PF  ClockGeneration.CLC_IRCLK (CGC10):
T__C10PF  ClockGeneration.CLC_ISCLK (CGC11):
T__C10PF  ClockGeneration.CLC_ITCLK (CGC12):
T__C33PF  ClockGeneration.CLC_DC_CLK (CGC13):
T__C10PF  ClockGeneration.CLC0 (CGC14):
T__C10PF  ClockGeneration.CLC1 (CGC15):
T__C10PF  ClockGeneration.CLC2 (CGC16):
T__C10PF  ClockGeneration.CLC3 (CGC17):
T__C10PF  ClockGeneration.CLC4 (CGC18):
T__C10PF  ClockGeneration.CLC5 (CGC19):
T__C10PF  ClockGeneration.CLC6 (CGC20):
T__C10PF  ClockGeneration.CLC7 (CGC21):
T__C10PF  ClockGeneration.CLC8 (CGC22):
T__C10PF  ClockGeneration.CLC9 (CGC23):
T__C10PF  ClockGeneration.CLC10 (CGC24):
T__C10PF  ClockGeneration.CLC11 (CGC25):
T__R10K  ClockGeneration.PulldownSyn_HPU (CGR25):
T__R4_7K  ClockGeneration.PullupOsc_BASE (CGR26):
T__R4_7K  ClockGeneration.PullupVB_OE (CGR27):
T__R1K  ClockGeneration.SeriesVCOK (CGR28):
T__MONOPIN25  ClockGeneration.Mono0 (CGMP1):
T__MONOPIN25  ClockGeneration.Mono1 (CGMP2):
T__MONOPIN25  ClockGeneration.Mono2 (CGMP3):
T__MONOPIN25  ClockGeneration.Mono3 (CGMP4):
T__MONOPIN25  ClockGeneration.Mono4 (CGMP5):
T__MONOPIN25  ClockGeneration.Mono5 (CGMP6):
T__MONOPIN25  ClockGeneration.Mono6 (CGMP7):
T__MONOPIN25  ClockGeneration.Mono7 (CGMP8):
T__MONOPIN25  ClockGeneration.Mono8 (CGMP9):
T__MONOPIN25  ClockGeneration.Mono9 (CGMP10):
T__MONOPIN25  ClockGeneration.Mono10 (CGMP11):
T__MONOPIN25  ClockGeneration.Mono11 (CGMP12):
T__MONOPIN25  ClockGeneration.Mono12 (CGMP13):
T__MONOPIN25  ClockGeneration.Mono13 (CGMP14):
T__MONOPIN25  ClockGeneration.Mono14 (CGMP15):
T__MONOPIN25  ClockGeneration.Mono15 (CGMP16):
T__MONOPIN25  ClockGeneration.Mono16 (CGMP17):
T__MONOPIN25  ClockGeneration.Mono17 (CGMP18):
T__MONOPIN25  ClockGeneration.Mono18 (CGMP19):
T__MONOPIN25  ClockGeneration.Mono19 (CGMP20):
T__MONOPIN25  ClockGeneration.Mono20 (CGMP21):
T__MONOPIN25  ClockGeneration.Mono21 (CGMP22):
T__MONOPIN25  ClockGeneration.Mono22 (CGMP23):
T__MONOPIN25  ClockGeneration.Mono23 (CGMP24):
T__MONOPIN25  ClockGeneration.Mono24 (CGMP25):
T__MONOPIN25  ClockGeneration.Mono25 (CGMP26):
T__MONOPIN25  ClockGeneration.Mono26 (CGMP27):
T__MONOPIN25  ClockGeneration.Mono27 (CGMP28):
T__MONOPIN25  ClockGeneration.Mono28 (CGMP29):
T__MONOPIN25  ClockGeneration.Mono29 (CGMP30):
T__MONOPIN25  ClockGeneration.Mono30 (CGMP31):
T__MONOPIN25  ClockGeneration.Mono31 (CGMP32):
T__MONOPIN25  ClockGeneration.Mono32 (CGMP33):
T__MONOPIN25  ClockGeneration.Mono33 (CGMP34):
T__MONOPIN25  ClockGeneration.Mono34 (CGMP35):
T__MONOPIN25  ClockGeneration.Mono35 (CGMP36):
T__MONOPIN25  ClockGeneration.Mono36 (CGMP37):
T__MONOPIN25  ClockGeneration.Mono37 (CGMP38):
T__MONOPIN25  ClockGeneration.Mono38 (CGMP39):
T__MONOPIN25  ClockGeneration.Mono39 (CGMP40):
T__MONOPIN25  ClockGeneration.Mono40 (CGMP41):
T__MONOPIN25  ClockGeneration.Mono41 (CGMP42):
T__MONOPIN25  ClockGeneration.Mono42 (CGMP43):
T__MONOPIN25  ClockGeneration.Mono43 (CGMP44):
T__MONOPIN25  ClockGeneration.Mono44 (CGMP45):
T__MONOPIN25  ClockGeneration.Mono45 (CGMP46):
T__MONOPIN25  ClockGeneration.Mono46 (CGMP47):
T__MONOPIN25  ClockGeneration.Mono47 (CGMP48):
T__MONOPIN25  ClockGeneration.Mono48 (CGMP49):
T__MONOPIN25  ClockGeneration.Mono49 (CGMP50):
T__MONOPIN25  ClockGeneration.Mono50 (CGMP51):
T__FERRITE120  ClockGeneration.Ferrite0 (CGL10):
T__FERRITE120  ClockGeneration.Ferrite1 (CGL11):
T__FERRITE120  ClockGeneration.Ferrite2 (CGL12):
T__FERRITE120  ClockGeneration.Ferrite3 (CGL13):
T__FERRITE120  ClockGeneration.Ferrite4 (CGL14):
T__FERRITE120  ClockGeneration.Ferrite5 (CGL15):
T__FERRITE120  ClockGeneration.Ferrite6 (CGL16):
T__FERRITE120  ClockGeneration.Ferrite7 (CGL17):
T__FERRITE120  ClockGeneration.Ferrite8 (CGL18):
T__FERRITE120  ClockGeneration.Ferrite9 (CGL19):
T__FERRITE120  ClockGeneration.Ferrite10 (CGL20):
T__FERRITE120  ClockGeneration.Ferrite11 (CGL21):
T__FERRITE120  ClockGeneration.Ferrite12 (CGL22):
T__FERRITE120  ClockGeneration.Ferrite13 (CGL23):
T__FERRITE120  ClockGeneration.Ferrite14 (CGL24):
T__FERRITE120  ClockGeneration.Ferrite15 (CGL25):
T__FERRITE120  ClockGeneration.Ferrite16 (CGL26):
T__CDC_POS  ClockGeneration.AVCC_CDC0 (CGCDC27):
T__CDC_POS  ClockGeneration.AVCC_CDC1 (CGCDC28):
T__CDC_POS  ClockGeneration.AVCC_CDC2 (CGCDC29):
T__CDC_POS  ClockGeneration.AVCC_CDC3 (CGCDC30):
T__CDC_POS  ClockGeneration.AVCC_CDC4 (CGCDC31):
T__CDC_POS  ClockGeneration.AVCC_CDC5 (CGCDC32):
T__CDC_POS  ClockGeneration.AVCC_CDC6 (CGCDC33):
T__CDC_POS  ClockGeneration.AVCC_CDC7 (CGCDC34):
T__CDC_POS  ClockGeneration.AVCC_CDC8 (CGCDC35):
T__CDC_POS  ClockGeneration.AVCC_CDC9 (CGCDC36):
T__CDC_POS  ClockGeneration.AVCC_CDC10 (CGCDC37):
T__CDC_POS  ClockGeneration.AVCC_CDC11 (CGCDC38):
T__CDC_POS  ClockGeneration.AVCC_CDC12 (CGCDC39):
T__CDC_POS  ClockGeneration.AVCC_CDC13 (CGCDC40):
T__CDC_POS  ClockGeneration.AVCC_CDC14 (CGCDC41):
T__CDC_POS  ClockGeneration.AVCC_CDC15 (CGCDC42):
T__CDC_POS  ClockGeneration.AVCC_CDC16 (CGCDC43):
T__CDC_POS  ClockGeneration.VC_CDC0 (CGCDC44):
T__CDC_POS  ClockGeneration.VC_CDC1 (CGCDC45):
T__CDC_POS  ClockGeneration.VC_CDC2 (CGCDC46):
T__CDC_POS  ClockGeneration.VC_CDC3 (CGCDC47):
T__CDC_POS  ClockGeneration.VC_CDC4 (CGCDC48):
T__CDC_POS  ClockGeneration.VC_CDC5 (CGCDC49):
T__CDC_POS  ClockGeneration.VC_CDC6 (CGCDC50):
T__CDC_POS  ClockGeneration.VC_CDC7 (CGCDC51):
T__CDC_POS  ClockGeneration.VC_CDC8 (CGCDC52):
T__CDC_POS  ClockGeneration.VC_CDC9 (CGCDC53):
T__CDC_POS  ClockGeneration.VC_CDC10 (CGCDC54):
T__CDC_POS  ClockGeneration.VC_CDC11 (CGCDC55):
T__CDC_POS  ClockGeneration.VC_CDC12 (CGCDC56):
T__CDC_POS  ClockGeneration.VC_CDC13 (CGCDC57):
T__CDC_POS  ClockGeneration.VC_CDC14 (CGCDC58):
T__CDC_POS  ClockGeneration.VC_CDC15 (CGCDC59):
T__CDC_POS  ClockGeneration.VC_CDC16 (CGCDC60):
T__CDC_POS  ClockGeneration.VC_CDC17 (CGCDC61):
T__CDC_POS  ClockGeneration.VC_CDC18 (CGCDC62):
T__CDC_POS  ClockGeneration.VC_CDC19 (CGCDC63):
T__CDC_POS  ClockGeneration.VC_CDC20 (CGCDC64):
T__CDC_POS  ClockGeneration.VC_CDC21 (CGCDC65):
T__CDC_POS  ClockGeneration.VC_CDC22 (CGCDC66):
T__CDC_POS  ClockGeneration.VC_CDC23 (CGCDC67):
T__CDC_POS  ClockGeneration.VC_CDC24 (CGCDC68):
T__CDC_POS  ClockGeneration.VC_CDC25 (CGCDC69):
T__CDC_POS  ClockGeneration.VC_CDC26 (CGCDC70):
T__CDC_POS  ClockGeneration.VC_CDC27 (CGCDC71):
T__CDC_POS  ClockGeneration.VC_CDC28 (CGCDC72):
T__CDC_POS  ClockGeneration.VC_CDC29 (CGCDC73):
T__CDC_POS  ClockGeneration.VC_CDC30 (CGCDC74):
T__CDC_POS  ClockGeneration.VC_CDC31 (CGCDC75):
T__CDC_POS  ClockGeneration.VC_CDC32 (CGCDC76):
T__CDC_POS  ClockGeneration.VC_CDC33 (CGCDC77):
T__CDC_POS  ClockGeneration.VC_CDC34 (CGCDC78):
T__CDC_POS  ClockGeneration.VC_CDC35 (CGCDC79):
T__CDC_POS  ClockGeneration.VC_CDC36 (CGCDC80):
T__CDC_POS  ClockGeneration.VC_CDC37 (CGCDC81):
T__CDC_POS  ClockGeneration.VC_CDC38 (CGCDC82):
T__CDC_POS  ClockGeneration.VC_CDC39 (CGCDC83):
T__CDC_POS  ClockGeneration.VC_CDC40 (CGCDC84):
T__CDC_POS  ClockGeneration.VC_CDC41 (CGCDC85):
T__CDC_POS  ClockGeneration.VC_CDC42 (CGCDC86):
T__CDC_POS  ClockGeneration.VC_CDC43 (CGCDC87):
T__CDC_POS  ClockGeneration.VC_CDC44 (CGCDC88):
T__CDC_POS  ClockGeneration.VC_CDC45 (CGCDC89):
T__CDC_POS  ClockGeneration.VC_CDC46 (CGCDC90):
T__CDC_POS  ClockGeneration.VC_CDC47 (CGCDC91):
T__CDC_POS  ClockGeneration.VC_CDC48 (CGCDC92):
T__CDC_POS  ClockGeneration.VC_CDC49 (CGCDC93):
T__CDC_POS  ClockGeneration.VC_CDC50 (CGCDC94):
T__CDC_POS  ClockGeneration.VC_CDC51 (CGCDC95):
T__CDC_POS  ClockGeneration.VC_CDC52 (CGCDC96):
T__CDC_POS  ClockGeneration.VC_CDC53 (CGCDC97):
T__CDC_POS  ClockGeneration.VC_CDC54 (CGCDC98):
T__CDC_POS  ClockGeneration.VC_CDC55 (CGCDC99):
T__CDC_POS  ClockGeneration.VC_CDC56 (CGCDC100):
T__CDC_POS  ClockGeneration.VC_CDC57 (CGCDC101):
T__CDC_POS  ClockGeneration.VC_CDC58 (CGCDC102):
T__CDC_POS  ClockGeneration.VC_CDC59 (CGCDC103):
T__CDC_POS  ClockGeneration.VC_CDC60 (CGCDC104):
T__CDC_POS  ClockGeneration.VC_CDC61 (CGCDC105):
T__CDC_POS  ClockGeneration.VC_CDC62 (CGCDC106):
T__CDC_POS  ClockGeneration.VC_CDC63 (CGCDC107):
T__CDC_POS  ClockGeneration.VC_CDC64 (CGCDC108):
T__CDC_POS  ClockGeneration.VC_CDC65 (CGCDC109):
T__CDC_POS  ClockGeneration.VC_CDC66 (CGCDC110):
T__CDC_POS  ClockGeneration.VC_CDC67 (CGCDC111):
T__CDC_POS  ClockGeneration.VC_CDC68 (CGCDC112):
T__CDC_POS  ClockGeneration.VC_CDC69 (CGCDC113):
T__CDC_POS  ClockGeneration.VC_CDC70 (CGCDC114):
T__CDC_POS  ClockGeneration.VC_CDC71 (CGCDC115):
T__TDC_POS  ClockGeneration.VC_TDC0 (CGTDC3):
T__TDC_POS  ClockGeneration.VC_TDC1 (CGTDC4):
T__TDC_POS  ClockGeneration.VC_TDC2 (CGTDC5):
T__CDC_POS  ClockGeneration.OSC_CDC0 (CGCDC116):
T__CDC_POS  ClockGeneration.OSC_CDC1 (CGCDC117):
T__CDC_POS  ClockGeneration.OSC_CDC2 (CGCDC118):
T__XC95144XL_100  ClockGeneration.NoisyPLD.Cpld (CGU1):
T__CDC_POS  ClockGeneration.NoisyPLD.VC_CDC0 (CGCDC1):
T__CDC_POS  ClockGeneration.NoisyPLD.VC_CDC1 (CGCDC2):
T__CDC_POS  ClockGeneration.NoisyPLD.VC_CDC2 (CGCDC3):
T__CDC_POS  ClockGeneration.NoisyPLD.VC_CDC3 (CGCDC4):
T__TDC_POS  ClockGeneration.NoisyPLD.VC_TDC0 (CGTDC1):
T__XC95144XL_100  ClockGeneration.QuietPLD.Cpld (CGU2):
T__CDC_POS  ClockGeneration.QuietPLD.VC_CDC0 (CGCDC5):
T__CDC_POS  ClockGeneration.QuietPLD.VC_CDC1 (CGCDC6):
T__CDC_POS  ClockGeneration.QuietPLD.VC_CDC2 (CGCDC7):
T__CDC_POS  ClockGeneration.QuietPLD.VC_CDC3 (CGCDC8):
T__TDC_POS  ClockGeneration.QuietPLD.VC_TDC0 (CGTDC2):
T__FS6377_01  ClockGeneration.Syn_RCLK.Syn (CGU3):
T__C220NF  ClockGeneration.Syn_RCLK.AC_Couple (CGC1):
T__R30  ClockGeneration.Syn_RCLK.SeriesTerm (CGR4):
T__FERRITE120  ClockGeneration.Syn_RCLK.Ferrite (CGL1):
T__CDC_POS  ClockGeneration.Syn_RCLK.VC_CDC0 (CGCDC9):
T__CDC_POS  ClockGeneration.Syn_RCLK.VC_CDC1 (CGCDC10):
T__FS6377_01  ClockGeneration.Syn_SCLK.Syn (CGU4):
T__C220NF  ClockGeneration.Syn_SCLK.AC_Couple (CGC2):
T__R30  ClockGeneration.Syn_SCLK.SeriesTerm (CGR5):
T__FERRITE120  ClockGeneration.Syn_SCLK.Ferrite (CGL2):
T__CDC_POS  ClockGeneration.Syn_SCLK.VC_CDC0 (CGCDC11):
T__CDC_POS  ClockGeneration.Syn_SCLK.VC_CDC1 (CGCDC12):
T__FS6377_01  ClockGeneration.Syn_TCLK.Syn (CGU5):
T__C220NF  ClockGeneration.Syn_TCLK.AC_Couple (CGC3):
T__R30  ClockGeneration.Syn_TCLK.SeriesTerm (CGR6):
T__FERRITE120  ClockGeneration.Syn_TCLK.Ferrite (CGL3):
T__CDC_POS  ClockGeneration.Syn_TCLK.VC_CDC0 (CGCDC13):
T__CDC_POS  ClockGeneration.Syn_TCLK.VC_CDC1 (CGCDC14):
T__FS6377_01  ClockGeneration.Syn_DCLK.Syn (CGU6):
T__C220NF  ClockGeneration.Syn_DCLK.AC_Couple (CGC4):
T__R30  ClockGeneration.Syn_DCLK.SeriesTerm (CGR7):
T__FERRITE120  ClockGeneration.Syn_DCLK.Ferrite (CGL4):
T__CDC_POS  ClockGeneration.Syn_DCLK.VC_CDC0 (CGCDC15):
T__CDC_POS  ClockGeneration.Syn_DCLK.VC_CDC1 (CGCDC16):
T__FS6377_01  ClockGeneration.Syn_DC_CLK.Syn (CGU7):
T__C220NF  ClockGeneration.Syn_DC_CLK.AC_Couple (CGC5):
T__R30  ClockGeneration.Syn_DC_CLK.SeriesTerm (CGR8):
T__FERRITE120  ClockGeneration.Syn_DC_CLK.Ferrite (CGL5):
T__CDC_POS  ClockGeneration.Syn_DC_CLK.VC_CDC0 (CGCDC17):
T__CDC_POS  ClockGeneration.Syn_DC_CLK.VC_CDC1 (CGCDC18):
T__FS6377_01  ClockGeneration.Syn_DX_CLK.Syn (CGU8):
T__C220NF  ClockGeneration.Syn_DX_CLK.AC_Couple (CGC6):
T__R30  ClockGeneration.Syn_DX_CLK.SeriesTerm (CGR9):
T__FERRITE120  ClockGeneration.Syn_DX_CLK.Ferrite (CGL6):
T__CDC_POS  ClockGeneration.Syn_DX_CLK.VC_CDC0 (CGCDC19):
T__CDC_POS  ClockGeneration.Syn_DX_CLK.VC_CDC1 (CGCDC20):
T__FS6377_01  ClockGeneration.Syn_HPU_CLK.Syn (CGU9):
T__C220NF  ClockGeneration.Syn_HPU_CLK.AC_Couple (CGC7):
T__R30  ClockGeneration.Syn_HPU_CLK.SeriesTerm (CGR10):
T__FERRITE120  ClockGeneration.Syn_HPU_CLK.Ferrite (CGL7):
T__CDC_POS  ClockGeneration.Syn_HPU_CLK.VC_CDC0 (CGCDC21):
T__CDC_POS  ClockGeneration.Syn_HPU_CLK.VC_CDC1 (CGCDC22):
T__FS6377_01  ClockGeneration.Syn_DPU_CLK.Syn (CGU10):
T__C220NF  ClockGeneration.Syn_DPU_CLK.AC_Couple (CGC8):
T__R30  ClockGeneration.Syn_DPU_CLK.SeriesTerm (CGR11):
T__FERRITE120  ClockGeneration.Syn_DPU_CLK.Ferrite (CGL8):
T__CDC_POS  ClockGeneration.Syn_DPU_CLK.VC_CDC0 (CGCDC23):
T__CDC_POS  ClockGeneration.Syn_DPU_CLK.VC_CDC1 (CGCDC24):
T__FS6377_01  ClockGeneration.Syn_DXINT_CLK.Syn (CGU11):
T__C220NF  ClockGeneration.Syn_DXINT_CLK.AC_Couple (CGC9):
T__R30  ClockGeneration.Syn_DXINT_CLK.SeriesTerm (CGR12):
T__FERRITE120  ClockGeneration.Syn_DXINT_CLK.Ferrite (CGL9):
T__CDC_POS  ClockGeneration.Syn_DXINT_CLK.VC_CDC0 (CGCDC25):
T__CDC_POS  ClockGeneration.Syn_DXINT_CLK.VC_CDC1 (CGCDC26):
T__CDC319  ClockGeneration.Drv_IRCLK.Drv (CGU27):
T__EXB2HV560JV  ClockGeneration.Drv_IRCLK.Term1 (CGRP1):
T__EXB2HV560JV  ClockGeneration.Drv_IRCLK.Term2 (CGRP2):
T__CDC319  ClockGeneration.Drv_ISCLK.Drv (CGU28):
T__EXB2HV560JV  ClockGeneration.Drv_ISCLK.Term1 (CGRP3):
T__EXB2HV560JV  ClockGeneration.Drv_ISCLK.Term2 (CGRP4):
T__CDC319  ClockGeneration.Drv_ITCLK.Drv (CGU29):
T__EXB2HV560JV  ClockGeneration.Drv_ITCLK.Term1 (CGRP5):
T__EXB2HV560JV  ClockGeneration.Drv_ITCLK.Term2 (CGRP6):
T__CDC319  ClockGeneration.Drv_SYN_BASE.Drv (CGU30):
T__EXB2HV560JV  ClockGeneration.Drv_SYN_BASE.Term1 (CGRP7):
T__EXB2HV560JV  ClockGeneration.Drv_SYN_BASE.Term2 (CGRP8):
T__R360  DataExchange.PullupDXF_HG0 (DXR4):
T__R360  DataExchange.PullupDXF_HG1 (DXR5):
T__R360  DataExchange.PullupDXF_HG2 (DXR6):
T__R360  DataExchange.PullupDXF_HG3 (DXR7):
T__R360  DataExchange.PullupDXC_A9 (DXR8):
T__R360  DataExchange.PullupDXC_A8 (DXR9):
T__R360  DataExchange.PullupDXC_A7 (DXR10):
T__R360  DataExchange.PullupDXC_A6 (DXR11):
T__R360  DataExchange.PullupDXC_B9 (DXR12):
T__R360  DataExchange.PullupDXC_B8 (DXR13):
T__R360  DataExchange.PullupDXC_B7 (DXR14):
T__R360  DataExchange.PullupDXC_B6 (DXR15):
T__R4_7K  DataExchange.PullupMRS (DXR16):
T__R4_7K  DataExchange.PullupWEN (DXR17):
T__R4_7K  DataExchange.PullupLD (DXR18):
T__XC2S150_PQ208  DataExchange.DXF_FPGA_A.Fpga.Fpga (DXU1):
T__R4_7K  DataExchange.DXF_FPGA_A.Fpga.INIT_Pullup (DXR1):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VC_CDC0 (DXCDC1):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VC_CDC1 (DXCDC2):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VC_CDC2 (DXCDC3):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VC_CDC3 (DXCDC4):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VC_CDC4 (DXCDC5):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VC_CDC5 (DXCDC6):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VC_CDC6 (DXCDC7):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VC_CDC7 (DXCDC8):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VB_CDC0 (DXCDC9):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VB_CDC1 (DXCDC10):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VB_CDC2 (DXCDC11):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VB_CDC3 (DXCDC12):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VB_CDC4 (DXCDC13):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VB_CDC5 (DXCDC14):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VB_CDC6 (DXCDC15):
T__CDC_POS  DataExchange.DXF_FPGA_A.Fpga.VB_CDC7 (DXCDC16):
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T__TDC_POS  DataExchange.DXF_FPGA_A.Fpga.VB_TDC0 (DXTDC2):
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T__R4_7K  DataExchange.DXF_FPGA_B.Fpga.INIT_Pullup (DXR2):
T__CDC_POS  DataExchange.DXF_FPGA_B.Fpga.VC_CDC0 (DXCDC17):
T__CDC_POS  DataExchange.DXF_FPGA_B.Fpga.VC_CDC1 (DXCDC18):
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T__CDC_POS  DataExchange.DXF_FPGA_B.Fpga.VB_CDC0 (DXCDC25):
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T__CDC_POS  DataExchange.DXF_FPGA_B.Fpga.VB_CDC2 (DXCDC27):
T__CDC_POS  DataExchange.DXF_FPGA_B.Fpga.VB_CDC3 (DXCDC28):
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T__CDC_POS  DataExchange.DXF_FPGA_B.Fpga.VB_CDC5 (DXCDC30):
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T__CDC_POS  DataExchange.DXF_FPGA_B.Fpga.VB_CDC7 (DXCDC32):
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T__TDC_POS  DataExchange.DXF_FPGA_B.Fpga.VB_TDC0 (DXTDC4):
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T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VC_CDC0 (DXCDC33):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VC_CDC1 (DXCDC34):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VC_CDC2 (DXCDC35):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VC_CDC3 (DXCDC36):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VC_CDC4 (DXCDC37):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VC_CDC5 (DXCDC38):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VC_CDC6 (DXCDC39):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VC_CDC7 (DXCDC40):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VB_CDC0 (DXCDC41):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VB_CDC1 (DXCDC42):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VB_CDC2 (DXCDC43):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VB_CDC3 (DXCDC44):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VB_CDC4 (DXCDC45):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VB_CDC5 (DXCDC46):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VB_CDC6 (DXCDC47):
T__CDC_POS  DataExchange.DXB_FPGA.Fpga.VB_CDC7 (DXCDC48):
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T__TDC_POS  DataExchange.DXB_FPGA.Fpga.VB_TDC0 (DXTDC6):
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T__CDC_POS  DataExchange.HostFIFO.VC_CDC0 (DXCDC49):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC1 (DXCDC50):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC2 (DXCDC51):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC3 (DXCDC52):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC4 (DXCDC53):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC5 (DXCDC54):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC6 (DXCDC55):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC7 (DXCDC56):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC8 (DXCDC57):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC9 (DXCDC58):
T__CDC_POS  DataExchange.HostFIFO.VC_CDC10 (DXCDC59):
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T__R360  DPU_Control.PullupDCC_A9 (DCR3):
T__R360  DPU_Control.PullupDCC_B10 (DCR4):
T__R360  DPU_Control.PullupDCC_B9 (DCR5):
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T__R4_7K  DPU_Control.DC_FPGA.Fpga.INIT_Pullup (DCR1):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VC_CDC0 (DCCDC1):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VC_CDC1 (DCCDC2):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VC_CDC2 (DCCDC3):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VC_CDC3 (DCCDC4):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VC_CDC4 (DCCDC5):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VC_CDC5 (DCCDC6):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VC_CDC6 (DCCDC7):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VC_CDC7 (DCCDC8):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VB_CDC0 (DCCDC9):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VB_CDC1 (DCCDC10):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VB_CDC2 (DCCDC11):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VB_CDC3 (DCCDC12):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VB_CDC4 (DCCDC13):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VB_CDC5 (DCCDC14):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VB_CDC6 (DCCDC15):
T__CDC_POS  DPU_Control.DC_FPGA.Fpga.VB_CDC7 (DCCDC16):
T__TDC_POS  DPU_Control.DC_FPGA.Fpga.VC_TDC0 (DCTDC1):
T__TDC_POS  DPU_Control.DC_FPGA.Fpga.VB_TDC0 (DCTDC2):
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T__JTAG_HEADER  FrontPanel.JTAG_Header (FPH2):
T__TTC_HEADER  FrontPanel.TTC_Header (FPH3):
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