//--------------------------------------------------------------------------- #pragma hdrstop //--------------------------------------------------------------------------- #include "spp.h" #include "views.h" #include "constraints.h" #include "DummyDevice.h" // for automated generation of dummy device files for layout application #include "CRB.h" #pragma argsused int main(int argc, char* argv[]) { try { TLogStatus Log( cout ); T_Root Root; // TRoot is always the highest-level module of a project Log << "Registering"; reg( Root ); // register highest-level module Log << "Connecting"; Root.ConnectAll(); // wire up hierarchy Log << "Assigning reference designators"; ifstream DSrce; DSrce.open( "OldDesignators.txt", ios_base::in | ios_base::nocreate ); // read in previously assigned designators, if any Root.ReadReferenceDesignators( DSrce ); DSrce.close(); Root.AssignReferenceDesignators(); Root.CheckReferenceDesignators(); // check for duplicates #if 1 // >>> write out all designators before layout commences ofstream DDest; DDest.open( "NewDesignators.txt", ios_base::out ); // write out designators for possible future use Root.WriteReferenceDesignators( DDest ); DDest.close(); #endif Log << "Filling netlist"; TNetList NetList; Root.FillNetList( &NetList ); Log << "Cleaning up netlist"; NetList.Cleanup(); // remove empty nets, add extensions to duplicate names, etc. Log << "Creating CAD netlist"; ofstream NetDest; NetDest.open( "CRB_PP_Netlist.txt", ios_base::out); Root.OutputCad3P( NetDest, &NetList ); // output in Allegro "third party" format Root.OutputCadPP( NetDest, &NetList ); // output in PADS PowerPCB format NetDest.close(); Log << "Creating bill of materials"; ofstream BOM_Dest; BOM_Dest.open( "temp.bom", ios_base::out); Root.OutputBOM( BOM_Dest ); // output bill of materials BOM_Dest.close(); #if 0 Log << "Creating constraint files"; // output constraint files TGenConstraints Constraints; Constraints.AddIgnorePort( "VCC", "VB", "GND" ); Constraints.AddIgnorePort( "TCK", "TMS", "TDI", "TDO" ); Constraints.AddIgnorePort( "PROGRAM_N" ); //Flash Subsystem PLD: do this first, because there are user I/O ports named CCLK and DIN Constraints.GenerateConstraintsFile( "FlashPldConstraints.ucf", &Root.VME_Interface.FlashPLD, &Root.VME_Interface.FlashPLD.Cpld ); Constraints.AddIgnorePort( "CCLK", "DIN" ); // now ignore CCLK and DIN on the remaining parts //Host PLD Constraints.GenerateConstraintsFile( "HostConstraints.ucf", &Root.Host.HOST_PLD, &Root.Host.HOST_PLD.Cpld ); //VME PLDs Constraints.GenerateConstraintsFile( "VMECPldConstraints.ucf", &Root.VME_Interface.VMEC_PLD, &Root.VME_Interface.VMEC_PLD.Cpld ); Constraints.GenerateConstraintsFile( "VMEDPldConstraints.ucf", &Root.VME_Interface.VMED_PLD, &Root.VME_Interface.VMED_PLD.Cpld ); //Clock Generation PLDS Constraints.GenerateConstraintsFile( "NoisyPldConstraints.ucf", &Root.ClockGeneration.NoisyPLD, &Root.ClockGeneration.NoisyPLD.Cpld ); Constraints.GenerateConstraintsFile( "QuietPldConstraints.ucf", &Root.ClockGeneration.QuietPLD, &Root.ClockGeneration.QuietPLD.Cpld ); Constraints.SetPinPrefix( "P" ); // FPGA's in PQFP's require a P before the pin number //DX FPGAs Constraints.GenerateConstraintsFile( "DXBFpgaConstraints.ucf", &Root.DataExchange.DXB_FPGA, &Root.DataExchange.DXB_FPGA.Fpga.Fpga ); Constraints.GenerateConstraintsFile( "DXFFpgaConstraints.ucf", &Root.DataExchange.DXF_FPGA_A, &Root.DataExchange.DXF_FPGA_A.Fpga.Fpga ); //Interconnect FPGAs Constraints.GenerateConstraintsFile( "BPIFpgaConstraints.ucf", &Root.Interconnect.BPI_FPGA[0], &Root.Interconnect.BPI_FPGA[0].Fpga.Fpga ); Constraints.GenerateConstraintsFile( "TTCFpgaConstraints.ucf", &Root.Interconnect.TTC_FPGA, &Root.Interconnect.TTC_FPGA.Fpga.Fpga ); //DPU Control FPGA Constraints.GenerateConstraintsFile( "DCFpgaConstraints.ucf", &Root.DPU_Control.DC_FPGA, &Root.DPU_Control.DC_FPGA.Fpga.Fpga ); #endif #if 0 // **** warning **** the specified device file directory must already exist Log << "Creating device files"; MakeDeviceFiles( &Root, "DeviceFiles" ); #endif Log << "Creating symbolic netlist"; ofstream View1_Dest; View1_Dest.open( "View1.txt", ios_base::out); TViewSymbolicNetlist View1; View1.ShowAllPins = true; View1.AddBriefNet( "/NC", "GND", "VCC5", "VCC3" ); // list some nets in non-verbose format View1.AddBriefNet( "TTC_L", "TTC_R" ); View1.Dump( View1_Dest, &Root, &NetList ); // output symbolic netlist view: parts and nets View1_Dest.close(); View1_Dest.open( "View1_nets.txt", ios_base::out); View1.DumpNets( View1_Dest, &Root, &NetList ); // output symbolic view: nets only View1_Dest.close(); View1_Dest.open( "View1_brief_nets.txt", ios_base::out); View1.DumpBriefNets( View1_Dest, &Root, &NetList ); // output symbolic view: brief nets only View1_Dest.close(); View1_Dest.open( "View1_parts.txt", ios_base::out); View1.DumpParts( View1_Dest, &Root ); // output symbolic view: parts only View1_Dest.close(); View1_Dest.open( "View1_modules.txt", ios_base::out); View1.DumpModules( View1_Dest, &Root ); // output symbolic view: modules only View1_Dest.close(); View1_Dest.open( "View1.html", ios_base::out); View1.DumpHTML( View1_Dest, &Root, &NetList ); // output symbolic view: HTML version View1_Dest.close(); /* Log << "Creating layout script files"; // output script (.do) files TGenLayoutScript LayoutScript; LayoutScript.GenerateScriptFile( &Root, &NetList ); */ Log << "Creating database dump"; ofstream Dest; Dest.open( "temp.txt", ios_base::out); DumpGlobals( Dest ); Root.DumpAll( Dest ); NetList.Dump( Dest ); TSubBusList NonListed; Root.AddNonListedPortRanges( &NonListed ); Dest << "\n\nThe entire range of all ports should be listed (i.e., connected):"; Dest << "\n Ports of TParts and TModules should be listed in the Part/Module's Owner's SubBusList or the Global SubBusList."; Dest << "\n Ports of TModules should also be listed in the Module's SubBusList, unless they are listed in the Global SubBusList."; Dest << "\n Ports of TCollection's are similar to ports of their ultimate owner TModule."; Dest << "\n\nTotal nonconforming port ranges: " << NonListed.GetSubBusCount(); if ( NonListed.GetSubBusCount() ) { Dest << " (listed below).\n"; NonListed.DumpAll( Dest ); } TNet NonWired; // form net containing all non-wired pins Root.AddNonWiredPins( &NetList, &NonWired ); Dest << "\n\nNon-wired pins:"; NonWired.DumpAsPortRanges( Dest ); // dump as PortRange's (rather than PinSpec's) for readability Dest << "\n\nSingle-node nets:"; int SingleNodeNets = DumpSingleNodeNets( &NetList, Dest ); Dest << "\n\nNo-connect net (" << NoConnect << "):"; int NoConnects = DumpNoConnectNet( &NetList, Dest ); Dest << "\n"; Dest << "\nTotal nonconforming port ranges: " << NonListed.GetSubBusCount() << "."; Dest << "\nTotal non-wired PinSpecs: " << NonWired.GetPinSpecCount() << "."; Dest << "\nTotal single-node nets: " << SingleNodeNets << "."; Dest << "\nTotal PinSpecs in no-connect net: " << NoConnects << "."; Dest << "\nTotal Nets: " << NetList.GetNetCount() << "."; Dest << "\n\nEnd of Dump\n"; Dest.close(); Log.End(); cout << "\nTotal nonconforming port ranges: " << NonListed.GetSubBusCount() << "."; cout << "\nTotal non-wired PinSpecs: " << NonWired.GetPinSpecCount() << "."; cout << "\nTotal single-node nets: " << SingleNodeNets << "."; cout << "\nTotal PinSpecs in no-connect net: " << NoConnects << "."; cout << "\nTotal Nets: " << NetList.GetNetCount() << "."; cout << "\n"; cout << "\nPress Enter to continue.\n" << flush; char c; cin >> noskipws >> c; } catch ( string& aString ) { cout << "\n\nError: " << aString << '\n'; if ( TModule::ConnectingModule ) { cout << "\nError detected while module " << *TModule::ConnectingModule << " was connecting.\n"; } char c; cin >> noskipws >> c; } return 0; } //---------------------------------------------------------------------------