#ifndef _CrbH_
#define _CrbH_

// Search all files for ">>>" to find important comments.

// CRB  ==  CSC ROD Backplane
// CSC  ==  Cathode Strip Chambers (for ATLAS Muon)
// ROD  ==  ReadOut Driver
// TIM  ==  TTC Interface Module
// TTC  ==  Timing, Trigger and Control (for ATLAS)
// IROD ==  Irvine ROD (designed at the University of California, Irvine)

// The CRB is a P5/P6/RP5/RP6 backplane that supports 16+ IROD's and one TIM


#include "spp.h"
#include "shorthand.h"
#include <iomanip.h>        // for setw()
                            // files needed by many of the subsystems
#include "CRB_Clones.h"     // cloned resisters, capacitors, etc.
#include "decoupling.h"

#include "CRB_RodSlot.h"    // subsystems
#include "CRB_TimSlot.h"
#include "CRB_Terminators.h"
#include "CRB_Power.h"


// ************  CRB  ************
// subsystem           abbreviation
// ------------        ------------
//   RodSlot             R05-R12, R14-R21
//   TimSlot             T13 or Tim
//   Terminators         TM  or Term
//   Power               PW

// Slot assignments:
//    Slot
//     1-3    no connector, slots are reserved for 6U boards
//       4    no connector, slot   is reserved for 6U/9U separator
//    5-12    R05-R12  (ROD's)
//      13    TIM
//   14-21    R14-R21  (ROD's)

// "TCLK Mapping Note" in CRB_TimSlot.h explains the mapping of TIM TCLK outputs to ROD TCLK inputs.


class T_Root : public TModule {
public:
// root-level module has no ports

// instantiate subsystems
  T_RodSlot          RodSlot[ 22 ]; // only 16 of these are registered (5-12, 14-21) -- non-registered RodSlot's are ignored
  T_TimSlot          TimSlot;
  T_Terminators      Terminators;
  T_Power            Power;



  virtual void Register() {
    ostringstream  RefBase;

    for ( int i =  5; i <= 21; ++ i ) {           // for each slot
      if ( i == 13 ) {                            // TIM is in slot 13
        Reg( &TimSlot, "TimSlot", i );            // register TimSlot as TimSlot13
        TimSlot.SetReferenceBase( "T13" );        // use T13 as the base for all of its reference designators
        continue;
      }
      Reg( &RodSlot[ i ], "RodSlot", i );                                      // register the RodSlot
      RefBase.str( "" );  RefBase << "R" << setw( 2 ) << setfill( '0' ) << i;  // set its reference base
      RodSlot[ i ].CopyReferenceBase( RefBase.str().c_str() );
    }
    reg(  Terminators     );  Terminators.SetReferenceBase(     "TM" );
    reg(  Power           );  Power.SetReferenceBase(           "PW" );
  }

  virtual void Connect() {

//*** connect supply ports ***//

    wireall( "VCC5"  );
    wireall( "VCC3"  );
    wireall( "GND" );

//*** connect remaining subsystem ports ***//

  // net names to override subsequently assigned net names
    "TTC_L" << TimSlot.Rod[  5 ].TTC;
    "TTC_R" << TimSlot.Rod[ 14 ].TTC;

  // connect ROD slots to TIM slot
    for ( int i = 5; i <= 21; ++i ) {             // for each slot
      if ( i == 13 )  continue;                   // skip Tim slot
      "R"  <<  TimSlot.Rod[ i ];
      TimSlot.Rod[ i ]  <<  RodSlot[ i ].Tim;
    }

  // connect terminators to TIM slot
    TimSlot.Term  <<  Terminators.Tim;

  }
};


#endif